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LTC1287 3V Single Chip 12-Bit Data Acquisition System
FEATURES
s s s
DESCRIPTIO
s
Single Supply 3.3V or 3.3V Operation Built-In Sample-and-Hold Direct 3-Wire Interface to Most MPU Serial Ports and All MPU Parallel Ports 30kHz Maximum Throughput Rate
KEY SPECIFICATIO S
s s s s
The LTC1287 is a 3V data acquisition component which contains a serial I/O successive approximation A/D converter. The device specifications are guaranteed at a supply voltage of 2.7V. It uses LTCMOSTM switched capacitor technology to perform a 12-bit unipolar, A/D conversion. The differential input has an on-chip sampleand-hold on the (+) input. The serial I/O is designed to communicate without external hardware to most MPU serial ports and all MPU parallel I/O ports allowing data to be transmitted and received over three wires. The low voltage operating capability and the low power consumption of this device make it ideally suited for battery applications. Given the ease of use, small package size and the minimum number of interconnects for I/O, the LTC1287 can be used for remote sensing applications.
LTCMOS is a trademark of Linear Technology Corporation
Minimum Guaranteed Supply Voltage: 2.7V Resolution: 12 Bits Fast Conversion Time: 24s Max Over Temp. Low Supply Current: 1.0mA
TYPICAL APPLICATI
s s s
Battery-Powered Instruments Data Logger Data Acquisition Modules
3V Differential Input Data Acquisition System
22F TANTALUM
+
1.0 CS DIFFERENTIAL INPUTS COMMON MODE RANGE 0V TO VCC* VCC 10k +IN LTC1287 -IN GND CLK DOUT VREF 22F TANTALUM ERROR (LSB) 0
+ -
3V LITHIUM
0.5
+
LT1004-1.2
-0.5
-1.0 0 TO AND FROM MPU * FOR OVERVOLTAGE PROTECTION, LIMIT THE INPUT CURRENT TO 15mA PER PIN OR CLAMP THE INPUTS TO VCC AND GND WITH 1N4148 DIODES. CONVERSION RESULTS ARE NOT VALID WHEN THE SELECTED CHANNEL OR OTHER CHANNEL IS OVERVOLTAGED (VIN < GND OR VIN > VCC). SEE SECTION ON OVERVOLTAGE PROTECTION IN THE APPLICATIONS INFORMATION. 512 1024 1536 2048 CODE
LTC1287 TA02
1287 TA01
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INL with VREF = 1.2V
2560 3072 3584 4096
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1
LTC1287 ABSOLUTE
(Notes 1 and 2)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW CS 1 +IN 2 -IN 3 GND 4 8 VCC 7 CLK 6 DOUT 5 VREF
Supply Voltage (VCC) to GND .................................. 12V Voltage Analog and Reference Inputs .... -0.3V to VCC + 0.3V Digital Inputs........................................ -0.3V to 12V Digital Outputs .......................... -0.3V to VCC + 0.3V Power Dissipation............................................. 500mW Operating Temperature Range LTC1287BI, LTC1287CI ................... - 40C TO 85C LTC1287BC, LTC1287CC ....................... 0C to 70C Storage Temperature Range ................ -65C to 150C Lead Temperature (Soldering, 10 sec.)................ 300C
ORDER PART NUMBER LTC1287BIJ LTC1287CIJ LTC1287BIN LTC1287CIN LTC1287BCJ LTC1287CCJ LTC1287BCN LTC1287CCN
J8 PACKAGE 8-LEAD CERAMIC DIP N8 PACKAGE 8-LEAD PLASTIC DIP
1287 PO
CO VERTER A D
PARAMETER Offset Error Linearity Error (INL) Gain Error Minimum Resolution for Which No Missing Codes are Guaranteed Analog and REF Input Range On Channel Leakage Current (Note 8)
ULTIPLEXER CHARACTERISTICS
CONDITIONS VCC = 2.7V (Note 4) VCC = 2.7V (Notes 4 & 5) VCC = 2.7V (Note 4)
q q q q
(Note 3) LTC1287C
MIN TYP MAX 3.0 0.5 1.0 12 UNITS LSB LSB LSB Bits V A A A A
LTC1287B
MIN TYP MAX 3.0 0.5 0.5 12
(Note 7) On Channel = 3V Off Channel = 0V On Channel = 0V Off Channel = 3V
q q q q
(V -) - 0.05V to VCC + 0.05V 1 1 1 1 1 1 1 1
Off Channel Leakage Current (Note 8)
On Channel = 3V Off Channel = 0V On Channel = 0V Off Channel = 3V
AC CHARACTERISTICS (Note 3)
SYMBOL fCLK tSMPL tCONV tCYC tdDO tdis ten PARAMETER Clock Frequency Analog Input Sample Time Conversion Time Total Cycle Time Delay Time, CLK to DOUT Data Valid Delay Time, CS to DOUT Hi-Z Delay Time, CLK to DOUT Enabled CONDITIONS (Note 6) See Operating Sequence See Operating Sequence See Operating Sequence (Note 6) See Test Circuits See Test Circuits See Test Circuits
q q q
LTC1287B/LTC1287C MIN TYP MAX (Note 9) 1.5 12 14 CLK+ 5.0s 250 80 130 450 160 250 0.5
UNITS MHz CLK Cycles CLK Cycles Cycles ns ns ns
2
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LTC1287 AC CHARACTERISTICS (Note 3)
SYMBOL thDO tf tr tWHCLK tWLCLK tsuCS tWHCS tWLCS CIN PARAMETER Time Output Data Remains Valid After CLK DOUT Fall Time DOUT Rise Time CLK High Time CLK Low Time Setup Time, CS Before CLK CS High Time Between Data Transfer Cycles CS Low Time During Data Transfer Input Capacitance See Test Circuits See Test Circuits VCC = 3V (Note 6) VCC = 3V (Note 6) VCC = 3V (Note 6) VCC = 3V (Note 6) VCC = 3V (Note 6) Analog Inputs On Channel Analog Inputs Off Channel Digital Inputs
q q
CONDITIONS
LTC1287B/LTC1287C MIN TYP MAX 50 40 40 600 800 100 5.0 14 100 5 5 100 100
UNITS ns ns ns ns ns ns s CLK Cycles pF pF pF
DIGITAL A D DC ELECTRICAL CHARACTERISTICS (Note 3)
SYMBOL VIH VIL IIH IIL VOH VOL IOZ ISOURCE ISINK ICC IREF PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage High Z Output Leakage Output Source Current Output Sink Current Positive Supply Current Reference Current CONDITIONS VCC = 3.6V VCC = 3.0V VIN = VCC VIN = 0V VCC = 3.0V, IO = 20A IO = 400A VCC = 3.0V, IO = 20A IO = 400A VOUT = VCC, CS High VOUT = 0V, CS High VOUT = 0V VOUT = VCC CS High VREF = 2.5V
q q q q q q q q q q
The q denotes specifications which apply over the operating temperature range; all other limits and typicals TA = 25C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground (unless otherwise noted). Note 3: VCC = 3V, VREF = 2.5V, CLK = 500kHz unless otherwise specified. Note 4: One LSB is equal to VREF divided by 4096. For example, when VREF = 2.5V, 1LSB = 2.5V/4096 = 0.61mV. Note 5: Integral nonlinearity error is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
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LTC1287B/LTC1287C MIN TYP MAX 2.1 0.45 2.5 -2.5 2.7 2.90 2.85 0.05 0.10 0.3 3 -3 -10 9 1.5 10 5 50
UNITS V V A A V V V V A A mA mA mA A
Note 6: Recommended operating conditions. Note 7: Two on-chip diodes are tied to each analog input which will conduct for analog voltages one diode drop below GND or one diode drop above VCC. Be careful during testing at low VCC levels, as high level analog inputs can cause this input diode to conduct, especially at elevated temperature, and cause errors for inputs near full scale. This spec allows 50mV forward bias of either diode. This means that as long as the analog input does not exceed the supply voltage by more than 50mV, the output code will be correct. Note 8: Channel leakage current is measured after the channel selection. Note 9: Increased leakage currents at elevated temperatures cause the S/ H to droop, therefore it is recommended that fCLK 30kHz at 85C and fCLK 3kHz at 25C.
3
LTC1287
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
2.8 2.6 2.4 CLK = 500kHz TA = 25C
OFFSET (LSB = 1/4096 x VREF)
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
LTC1287 G1
Change in Linearity vs Reference Voltage
CHANGE IN LINEARITY (LSB = 1/4096 x VREF)
0.5
CHANGE IN GAIN (LSB = 1/4096 x VREF)
MAGNITUDE OF OFFSET CHANGE (LSB)
VCC = 3V 0.4
0.3
0.2
0.1
0
0
0.5
2.5 1.0 1.5 2.0 REFERENCE VOLTAGE (V)
Change in Linearity vs Temperature
0.5 0.5
MAGNITUDE OF GAIN CHANGE (LSB)
MAGNITUDE OF LINEARITY CHANGE (LSB)
DOUT DELAY TIME FROM CLK (ns)
0.4
VCC = 3V VREF = 2.5V CLK = 500kHz
0.3
0.2
0.1
0 40 20 0 60 - 40 - 20 80 AMBIENT TEMPERATURE (C)
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UW
3.0
LTC1287 G4
Supply Current vs Temperature
1.9 1.8 1.7 1.6 1.5 1.4 1.3 -40 -25 -10 CLK = 500kHz VCC = 3V
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
Unadjusted Offset Voltage vs Reference Voltage
VCC = 3V
VOS = 0.250mV
VOS = 0.125mV
5 20 35 50 65 TEMPERATURE (C)
80
95
0
0.5
2.5 1.0 1.5 2.0 REFERENCE VOLTAGE (V)
3.0
LTC1287 G2
LTC1287 G3
Change in Gain vs Reference Voltage
0 VCC = 3V
0.5
Change in Offset vs Temperature
VCC = 3V VREF = 2.5V CLK = 500kHz
-0.1
0.4
-0.2
0.3
-0.3
0.2
-0.4
0.1
-0.5
0
0.5
2.5 1.0 1.5 2.0 REFERENCE VOLTAGE (V)
3.0
0 40 20 0 60 -40 - 20 80 AMBIENT TEMPERATURE (C)
100
LTC1287 G5
LTC1287 G6
Change in Gain vs Temperature
350
DOUT Delay Time vs Temperature
VCC = 3V 300 MSB-FIRST DATA 250 200 LSB-FIRST DATA 150 100 50 0 -40 -20
0.4
VCC = 3V VREF = 2.5V CLK = 500kHz
0.3
0.2
0.1
100
0 40 20 0 60 -40 -20 80 AMBIENT TEMPERATURE (C)
100
40 80 20 60 0 AMBIENT TEMPERATURE (C)
100
LTC1287 G7
LTC1287 G8
LTC1287 G9
LTC1287
TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Clock Rate vs Source Resistance
500
MAXIMUM CLK FREQUENCY* (MHz)
MINIMUM CLK FREQUENCY (MHz)
MAXIMUM RFILTER*** ()
400
VCC = 3V VREF = 2.5V CLK = 500kHz
300
200
+VIN +IN -IN
100
RSOURCE-
0 100
1k 10k RSOURCE - ()
Sample-and-Hold Acquisition Time vs Source Resistance
100 1000
S & H ACQUISITION TIME TO 0.02% (s)
800 700 600 500 400 300 200 100 ON CHANNEL OFF CHANNEL
PEAK-TO-PEAK NOISE ERROR (LSB)
VREF = 2.5V VCC = 3V TA = 25C 0V TO 2.5V INPUT STEP
RSOURCE+
INPUT CHANNEL LEAKAGE CURRENT (nA)
10
VIN
+ -
1 100
1k RSOURCE+ ()
*
MAXIMUM CLK FREQUENCY REPRESENTS THE CLK FREQUENCY AT WHICH A 0.1LSB SHIFT IN THE ERROR AT ANY CODE TRANSITION FROM ITS 500kHz VALUE IS FIRST DETECTED. AS THE CLK FREQUENCY IS DECREASED FROM 1MHz, MINIMUM CLK FREQUENCY (ERROR 0.1LSB) REPRESENTS THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 500kHz VALUE IS FIRST DETECTED.
**
PI FU CTIO S
#
1 2, 3 4 5 6 7 8
PIN
CS +IN, -IN GND VREF DOUT CLK VCC
FUNCTION
Chip Select Input Analog Inputs Analog Ground Reference Input Digital Data Output Shift Clock Positive Supply
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LTC G10
Minimum Clock Rate for 0.1LSB Error**
10k VCC = 3V 0.25 1k 0.20 0.15 0.10 0.05 1
Maximum Filter Resistor vs Cycle Time
RFILTER VIN CFILTER 1F
+ -
100
10
100k
-50
0 25 50 75 -25 AMBIENT TEMPERATURE (C)
100
10
100 1000 CYCLE TIME (s)
10000
LTC1287 G12
LTC1287 G11
Input Channel Leakage Current vs Temperature
1.0
GUARANTEED 900
Noise Error vs Reference Voltage
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 2.5 1.5 2.0 1.0 REFERENCE VOLTAGE (V) 3.0 LTC1287 NOISE = 200VP-P
10k
LTC1287 G13
0 -50 -30 -10 10 30 50 70 90 110 130 AMBIENT TEMPERATURE (C)
LTC1287 G14
LTC1287 G15
*** MAXIMUM RFILTER REPRESENTS THE FILTER RESISTOR VALUE AT WHICH A 0.1LSB CHANGE IN FULL SCALE ERROR FROM ITS VALUE AT RFILTER = 0 IS FIRST DETECTED.
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DESCRIPTION
A logic low on this input enables the LTC1287. These inputs must be free of noise with respect to GND. GND should be tied directly to an analog ground plane. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. The A/D conversion result is shifted out of this output. This clock synchronizes the serial data transfer. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
5
LTC1287
BLOCK DIAGRA
VCC 8
INPUT SHIFT REGISTER 2 3 ANALOG INPUT MUX
+IN -IN
4 GND
TEST CIRCUITS
On and Off Channel Leakage Current
3V ION A IOFF A OFF CHANNEL
DOUT 0.6V
LTC1287 TC03
POLARITY
LTC1287 TC1
Load Circuit for tdis and ten
TEST POINT
3k DOUT 100pF
Load Circuit for tdDO, tr and tf
1.5V
DOUT 100pF
6
W
7 CLK OUTPUT SHIFT REGISTER SAMPLE AND HOLD 6 DOUT COMP 12-BIT SAR 12-BIT CAPACITIVE DAC 5 VREF CONTROL AND TIMING 1 CS
LTC1287 BD
Voltage Waveforms for DOUT Delay Time, tdDO
CLK 0.45V
ON CHANNEL
tdDO 2.1V
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
DOUT 2.1V 0.6V tr
3V tdis WAVEFORM 2, ten tdis WAVEFORM 1
LTC1287 TC05
tf
LTC1287 TC04
Voltage Waveforms for tdis
CS 2.1V
DOUT WAVEFORM 1 (SEE NOTE 1) tdis DOUT WAVEFORM 2 (SEE NOTE 2)
90%
3k TEST POINT
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
LTC1287 TC02
LTC1287 TC06
LTC1287 TEST CIRCUITS
Voltage Waveforms for ten
CS
CLK
DOUT ten
B11 0.6V
LTC1287 TC07
APPLICATI
S I FOR ATIO
The LTC1287 is a data acquisition component which contains the following functional blocks: 1. 12-bit successive approximation capacitive A/D converter 2. Analog multiplexer (MUX) 3. Sample-and-hold (S/H) 4. Synchronous, half-duplex serial interface 5. Control and timing logic DIGITAL CONSIDERATIONS Serial Interface The LTC1287 communicates with microprocessors and other external circuitry via a synchronous, half-duplex, three-wire serial interface (see Operating Sequence). The clock (CLK) synchronizes the data transfer with each bit being transmitted on the falling CLK edge. The LTC1287
tCYC CS
CLK Hi-Z DOUT tSMPL
B11 B10
B9
B8
B7
B6
B5
B4
B3
tCONV
Figure 1. LTC1287 Operating Sequence
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does not require a configuration input word and has no DIN pin. It is permanently configured to have a single differential input and to operate in unipolar mode. A falling CS initiates data transfer. The first CLK pulse enables DOUT. After one null bit, the A/D conversion result is output on the DOUT line with a MSB-first sequence followed by a LSBfirst sequence. With the half duplex serial interface the DOUT data is from the current conversion. This provides easy interface to MSB- or LSB-first serial ports. Bringing CS high resets the LTC1287 for the next data exchange. Logic Levels The logic level standards for this supply range have not been well defined. What standards that do exist are not universally accepted. The trip point on the logic inputs of the LTC1287 is 0.28 x VCC. This makes the logic inputs compatible with HC-type levels and processors that are
B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 tSMPL
LTC1287 F01
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LTC1287
APPLICATI
S I FOR ATIO
specified at 3.3V. The output DOUT is also compatible with the above standards. The following summarizes such levels. VCC - 0.1V VOH (no load) VOL (no load) 0.1V VOH 0.9 x VCC VOL 0.1 x VCC VIH 0.7 x VCC VIL 0.2 x VCC The LTC1287 can be driven with 5V logic even when VCC is at 3.3V. This is due to a unique input protection device that is found on the LTC1287. Microprocessor Interfaces The LTC1287 can interface directly (without external hardware) to most popular microprocessor (MPU) synchronous serial formats. If an MPU without a serial interface is used, then three of the MPU's parallel port lines can be programmed to form the serial link to the LTC1287. Many of the popular MPUs can operate with 3V supplies. For example the MC68HC11 is an MPU with a serial format (SPI). Likewise parallel MPUs that have the 8051 type architecture are also capable of operating at this voltage range. The code for these processors remains the same and can be found in the LTC1292 data sheet. Sharing the Serial Interface The LTC1287 can share the same two-wire serial interface with other peripheral components or other LTC1287s (Figure 2). In this case, the CS signals decide which LTC1287 is being addressed by the MPU.
2
1
0 2-WIRE SERIAL INTERFACE TO OTHER PERIPHERALS OR LTC1287s CS LTC1287 2 CHANNELS
1 2 LTC1287 3 6 5
LTC1287 F03/DB
OUTPUT PORT SERIAL DATA 2 2 CS LTC1287 2 CHANNELS 2 CS LTC1287 2 CHANNELS 2
MPU
Figure 2. Several LTC1287s Sharing One 2-Wire Serial Interface
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ANALOG CONSIDERATIONS Grounding The LTC1287 should be used with an analog ground plane and single point grounding techniques. Do not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance use a PC board. The ground pin (Pin 4) should be tied directly to the ground plane with minimum lead length (a low profile socket is fine). Pin 7 (VCC) should be bypassed to the ground plane with a 22F (minimum value) tantalum with leads as short as possible and as close as possible to the pin. A 0.1F ceramic disk also should be placed in parallel with the 22F and again with leads as short as possible and as close to VCC as possible. Figure 3 shows an example of an ideal LTC1287 ground plane design for a two-sided board. Of course this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible. Bypassing For good performance, VCC must be free of noise and ripple. Any changes in the VCC voltage with respect to ground during a conversion cycle can induce errors or noise in the output code. VCC noise and ripple can be kept below 0.5mV by bypassing the VCC pin directly to the analog plane with a minimum of 22F tantalum capacitor and with leads as short as possible. The lead from the device to the VCC supply also should be kept to a minimum and the VCC supply should have a low output impedance
0.1F VCC 22F TANTALUM 8 7 4
LTC1287 F02
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Figure 3. Example Ground Plane for the LTC1287
LTC1287
APPLICATI S I FOR ATIO U
5V/DIV CS 0.5mV/DIV VCC HORIZONTAL: 20s/DIV
such as obtained from a voltage regulator (e.g., LT1117). For high frequency bypassing a 0.1F ceramic disk placed in parallel with the 22F is recommended. Again the leads should be kept to a minimum. Using a battery to power the LTC1287 will help reduce the amount of bypass capacitance required on the VCC pin. A battery placed close to the device will only require 10F to adequately bypass the supply pin. Figure 4 shows the effect of poor VCC bypassing. Figure 5 shows the settling of a LT1117 low dropout regulator with a 22F bypass capacitor. The noise and ripple is kept around 0.5mV. Figure 6 shows the response of a lithium battery with a 10F bypass capacitor. The noise and ripple is kept below 0.5mV. Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1287 have
VERTICAL: 0.5mV/DIV
HORIZONTAL: 10s/DIV
Figure 4. Poor VCC Bypassing. Noise and Ripple Can Cause A/D Errors
5V/DIV
0.5mV/DIV
HORIZONTAL: 20s/DIV
Figure 5. LT1117 Regulator with 22F Bypassing on VCC
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Figure 6. Lithium Battery with 10F Bypassing on VCC
capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem. If large source resistances are used or if slow settling op amps drive the inputs, take care to insure the transients caused by the current spikes settle completely before the conversion begins. Source Resistance The analog inputs of the LTC1287 look like a 100pF capacitor (CIN) in series with a 1.5k resistor (RON). This value for RON is for VCC = 2.7V. With larger supply voltages RON will be reduced. For example, with VCC = 2.7V and V - = - 2.7V, RON becomes 500. CIN gets switched between (+) and (-) inputs once during each conversion cycle. Large external source resistors and capacitances will slow the settling of the inputs. It is important that the overall RC time constant is short enough to allow the analog inputs to settle completely within the allowed time.
"+" INPUT LTC1287 C1 "-" INPUT CS RON = 1.5k tWHCS + 1/2 CLK CIN = 100pF
RSOURCE + VIN +
CS
RSOURCE - VIN -
VCC
C2
LTC1287 F07
Figure 7. Analog Input Equivalent Circuit
9
LTC1287
APPLICATI S I FOR ATIO U
resistance must be used, the sample time can be increased by using a slower CLK frequency. With the minimum possible sample time of 6.0s, RSOURCE+ < 4.0k and C1 < 20pF will provide adequate settle time. "-" Input Settling At the end of the sample phase the input capacitor switches to the "-" input and the conversion starts (see Figures 8a, 8b and 8c). During the conversion, the "+" input voltage is
tSUCS tSMPL (+) INPUT MUST SETTLE DURING THIS TIME DOUT HI-Z
1ST BIT TEST (-) INPUT MUST SETTLE DURING THIS TIME
"+" Input Settling The input capacitor is switched onto the "+" input during the sample phase (tSMPL, see Figures 8a, 8b and 8c). The sample period can be as short as tWHCS + 0.5 CLK cycle or as long as tWHCS + 1.5 CLK cycles before a conversion starts. This variability depends on where CS falls relative to CLK. The voltage on the "+" input must settle completely within the sample period. Minimizing RSOURCE+ and C1 will improve the settling time. If large "+" input source
CS
CLK
(+) INPUT
(-) INPUT
tWHCS CS
CLK tSMPL (+) INPUT MUST SETTLE DURING THIS TIME DOUT B11 HI-Z
1ST BIT TEST (-) INPUT MUST SETTLE DURING THIS TIME
(+) INPUT
(-) INPUT
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"+" and "-" Input Settling Windows
tWHCS
B11
B10
B9
Figure 8a. Setup Time (tSUCS) is Met
LTC1287 F8a
B10
B9
Figure 8b. Setup Time (tSUCS) is Met
LTC1287 F8b
LTC1287
APPLICATI S I FOR ATIO
tWHCS CS
CLK tSMPL (+) INPUT MUST SETTLE DURING THIS TIME DOUT B11 HI-Z
1ST BIT TEST (-) INPUT MUST SETTLE DURING THIS TIME
(+) INPUT
(-) INPUT
LTC1287 F8c
Figure 8c. Setup Time (tSUCS) is Not Met
effectively "held" by the sample and hold and will not affect the conversion result. It is critical that the "-" input voltage be free of noise and settle completely during the first CLK cycle of the conversion. Minimizing RSOURCE - and C2 will improve settling time. If large "-" input source resistance must be used the time can be extended by using a slower CLK frequency. At the maximum CLK frequency of 500kHz, RSOURCE - < 200 and C2 < 20pF will provide adequate settling. Input Op Amps When driving the analog inputs with an op amp it is important that the op amp settles within the allowed time
VERTICAL: 5mV/DIV
HORIZONTAL: 500ns/DIV
VERTICAL: 5mV/DIV
Figure 9. Adequate Settling of Op Amp Driving Analog Input
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(see Figures 8a, 8b and 8c). Again the "+" and "-" input sampling times can be extended as described above to accommodate slower op amps. For single supply low voltage application the LT1006, LT1013 and LT1014 can be made to settle well even with the minimum settling windows of 6s ("+" input) and 2s ("-" input) which occur at the maximum clock rates (CLK = 500kHz). Figures 9 and 10 show examples of adequate and poor op amp settling. The LT1077, LT1078 or LT1079 can be used here to reduce power consumption. Placing an RC network at the output of the op amps will inprove the settling response and also reduce the broadband noise.
HORIZONTAL: 20s/DIV
Figure 10. Poor Op Amp Settling Can Cause A/D Errors
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LTC1287
APPLICATI S I FOR ATIO U
Acquisition Time vs Source Resistance). The input voltage is sampled during the tSMPL time as shown in Figure 8. The sampling interval begins at rising edge of CS and continues until the falling edge of the CLK before the conversion begins. On this falling edge the S&H goes into the hold mode and the conversion begins. Differential Input With a differential input the A/D no longer converts a single voltage but converts the difference between two voltages. The voltage on the +IN pin is sampled and held and can be rapidly time varying. The voltage on the -IN pin must remain constant and be free of noise and ripple throughout the conversion time. Otherwise the differencing operation will not be done accurately. The conversion time is 12 CLK cycles. Therefore a change in the -IN input voltage during this interval can cause conversion errors. For a sinusoidal voltage on the -IN input this error would be:
12 VERROR(MAX) = 2f(-IN)VPEAK f CLK
RC Input filtering It is possible to filter the inputs with an RC network as shown in Figure 11. For large values of CF (e.g., 1F) the capacitive input switching currents are averaged into a net DC current. A filter should be chosen with a small resistor and large capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximately IDC = 100pF x VIN/tCYC and is roughly proportional to VIN. When running at the minimum cycle time of 33s, the input current equals 7.6A at VIN = 2.5V. Here a filter resistor of 8 will cause 0.1LSB of full-scale error. If a large filter resistor must be used, errors can be reduced by increasing the cycle time as shown in the Typical Performance Characteristics curve Maximum Filter Resistor vs Cycle Time.
RFILTER VIN - CFILTER IDC "+" LTC1287 "-"
Figure 11. RC Input Filtering
Input Leakage Current Input leakage currents also can create errors if the source resistance gets too large. For example, the maximum input leakage specification of 1A (at 85C) flowing through a source resistance of 1k will cause a voltage drop of 1mV or 1.6LSB with VREF = 2.5V. This error will be much reduced at lower temperatures because leakage drops rapidly (see Typical Performance Characteristics curve Input Channel Leakage Current vs Temperature). SAMPLE-AND-HOLD Single-Ended Input The LTC1287 provides a built-in sample and hold (S&H) function on the +IN input for signals acquired in the single ended mode (-IN pin grounded). The sample and hold allows the LTC1287 to convert rapidly varying signals (see Typical Performance Characteristics curve of S&H
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LTC1287 F11
Where f(-IN) is the frequency of the -IN input voltage, VPEAK is its peak amplitude and fCLK is the frequency of the CLK. Usually VERROR will not be significant. For a 60Hz signal on the -IN input to generate a 0.25LSB error (150V) with the converter running at CLK = 500kHz, its peak value would have to be 16mV. Rearranging the above equation, the maximum sinusoidal signal that can be digitized to a given accuracy is given as: VERROR(MAX) fCLK f(- IN) MAX = 2 VPEAK 12 For 0.25LSB error (150V) the maximum input sinusoid with a 2.5V peak amplitude that can be digitized is 0.4Hz. Reference Input The voltage on the reference input of the LTC1287 determines the voltage span of the A/D converter. The reference input has transient capacitive switching currents due to the switched capacitor conversion technique (see Figure 12). During each bit test of the
LTC1287
APPLICATI
S I FOR ATIO
conversion (every CLK cycle) a capacitive current spike will be generated on the reference pin by the A/D. These current spikes settle quickly and do not cause a problem. If slow settling circuitry is used to drive the reference input, take care to insure that transients caused by these current spikes settle completely during each bit test of the conversion.
REF+ 14 ROUT VREF GND 13 LTC1287 EVERY CLK CYCLE RON 8pF - 40pF
LTC 1287 F12
Figure 12. Reference Input Equivalent Circuit
VERTICAL: 0.5mV/DIV
HORIZONTAL: 1s/DIV
Figure 13. Adequate Reference Settling
VERTICAL: 0.5mV/DIV
HORIZONTAL: 10s/DIV
Figure 14. Poor Reference Settling Can Cause A/D Errors
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Figures 13 and 14 show examples of both adequate and poor settling. Using a slower CLK will allow more time for the reference to settle. Even at the maximum CLK rate of 500kHz most references and op amps can be made to settle within the 2s bit time. For example an LT1019 used in the shunt mode with a 10F bypass capacitor will settle adequately. To minimize power an LT1004-2.5 can be used with a 10F bypass capacitor. For lower value references the LT1004-1.2 with a 10F bypass capacitor can be used. Reduced Reference Operation The effective resolution of the LTC1287 can be increased by reducing the input span of the converter. The LTC1287 exhibits good linearity over a range of reference voltages (seeTypical Performance Characteristics curves of Change in Linearity vs Reference Voltage). Care must be taken when operating at low values of VREF because of the reduced LSB step size and the resulting higher accuracy requirement placed on the converter. Offset and Noise are factors that must be considered when operating at low VREF values. Offset with Reduced VREF The offset of the LTC1287 has a larger effect on the output code when the A/D is operated with a reduced reference voltage. The offset (which is typically a fixed voltage) becomes a larger fraction of an LSB as the size of the LSB is reduced. The Typical Performance Characteristics curve of Unadjusted Offset Error vs Reference Voltage shows how offset in LSBs is related to reference voltage for a typical value of VOS. For example a VOS of 0.1mV, which is 0.2LSB with a 2.5V reference becomes 0.4LSB with a 1.25 reference. If this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the -IN input to the LTC1287. Noise with Reduced VREF The total input referred noise of the LTC1287 can be reduced to approximately 200V peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. This
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the limit on the resistor value is the MSB bit test is affected by the value of the resistor placed at the -IN input (see discussion on Analog Inputs and the Typical Performance Characteristics curve of Maximum CLK Frequency vs Source Resistance). If VCC and VREF are not tied together, then VCC should be turned on first, then VREF. If this sequence cannot be met, connecting a diode from VREF to VCC is recommended (see Figure 18). Because a unique input protection structure is used on the digital input pins, the signal levels on these pins can exceed the device VCC without damaging the device.
1N4148 DIODES CS +IN +3V VCC CLK LTC1287 -IN DOUT GND VREF
LTC1287 F15
noise is insignificant with a 2.5V reference input but will become a larger fraction of an LSB as the size of the LSB is reduced. The Typical Performance Characteristics curve of Noise Error vs Reference Voltage shows the LSB contribution of this 200V of noise. For operation with a 2.5V reference, the 200V noise is only 0.32LSB peak-to-peak. Here the LTC1287 noise will contribute virtually no uncertainty to the output code. For reduced references, the noise may become a significant fraction of an LSB and cause undesirable jitter in the output code. For example, with a 1.25V reference, this 200V noise is 0.64LSB peak-to-peak. This will reduce the range of input voltages over which a stable output code can be achieved by 0.64LSB. Now averaging readings may be necessary. This noise data was taken in a very clean test fixture. Any setup induced noise (noise or ripple on VCC, VREF or VIN) will add to the internal noise. The lower the reference voltage used, the more critical it becomes to have a noise-free setup. Overvoltage Protection Applying signals to the LTC1287's analog inputs that exceed the positive supply or that go below ground will degrade the accuracy of the A/D and possibly damage the device. For example this condition would occur if a signal is applied to the analog inputs before power is applied to the LTC1287. Another example is the input source operating from different supplies of larger value than the LTC1287. These conditions should be prevented either with proper supply sequencing or by use of external circuitry to clamp or current limit the input source. There are two ways to protect the inputs. In Figure 15 diode clamps from the inputs to VCC and GND are used. The second method is to put resistors in series with the analog inputs for current limiting. Limit the current to 15mA per channel. The +IN input can accept a resistor value of 1k but the -IN input cannot accept more than 200 when clocked at its maximum clock frequency of 500kHz. If the LTC1287 is clocked at the maximum clock frequency and 200 is not enough to current limit the input source then the clamp diodes are recommended (Figures 16 and 17). The reason for
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Figure 15. Overvoltage Protection for Inputs
CS 1k +IN 200
VCC CLK
+3V
LTC1287 -IN DOUT GND VREF
LTC1287 F16
Figure 16. Overvoltage Protection for Inputs
1N4148 DIODES CS 1k +IN -IN GND CLK LTC1287 DOUT VREF
LTC1287 F17
VCC
+3V
Figure 17. Overvoltage Protection for Inputs
LTC1287
APPLICATI S I FOR ATIO
VCC CLK 1N4148 +3V
CS +IN
LTC1287 -IN DOUT GND VREF
+2.5V
LTC1287 F18
Figure 18
22F TANTALUM +3V f/32
CS VIN +IN -IN
VCC CLK LTC1287 DOUT VREF f
GND
TO OSCILLOSCOPE
Figure 19. "Quick Look" Circuit for the LTC1287
CLK
CS
DOUT
NULL MSB LSB LSB DATA BIT (B11) (B0) (B1) VERTICAL: 5V/DIV HORIZONTAL: 5s/DIV
Figure 20. Scope Trace of the LTC1287 "Quick Look" Circuit Showing A/D Output 1010101010 (AAAHEX)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.
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A "Quick Look" Circuit for the LTC1287 Users can get a quick look at the function and timing of the LTC1287 by using the following simple circuit (Figure 19). VREF is tied to VCC. VIN is applied to the +IN input and the -IN input is tied to the ground plane. CS is driven at 1/32 the clock rate by the 74HC393 and DOUT outputs the data. The output data from the DOUT pin can be viewed on an oscilloscope that is set up to trigger on the falling edge of CS (Figure 20). Note the LSB data is partially clocked out before CS goes high.
A1 CLR1 1QA 1QB 1QC 1QD GND VCC A2 CLR2 74HC393 2QA 2QB 2QC 2QD 0.1F CLOCK IN 500kHz
LTC1287 F19
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15
LTC1287
PACKAGE DESCRIPTIO
0.290 - 0.320 (7.366 - 8.128)
0.008 - 0.018 (0.203 - 0.460) 0.385 0.025 (9.779 0.635)
0 - 15 1 0.038 - 0.068 (0.965 - 1.727) 0.014 - 0.026 (0.360 - 0.660) 0.125 3.175 0.100 0.010 MIN (2.540 0.254) 0.055 (1.397) MAX 2 3 4
J8 0392
0.300 - 0.320 (7.620 - 8.128)
0.009 - 0.015 (0.229 - 0.381)
0.065 (1.651) TYP 0.125 (3.175) MIN 0.020 (0.508) MIN
(
+0.025 0.325 -0.015 +0.635 8.255 -0.381
)
0.045 0.015 (1.143 0.381) 0.100 0.010 (2.540 0.254)
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977
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Dimensions in inches (millimeters) unless otherwise noted. J8 Package 8-Lead Ceramic DIP
0.200 (5.080) MAX 0.015 - 0.060 (0.381 - 1.524) 0.005 (0.127) MIN 0.405 (10.287) MAX 8 7 6 5
0.025 (0.635) RAD TYP
0.220 - 0.310 (5.588 - 7.874)
TJMAX 150C
JA 100C/W
N8 Package 8-Lead Plastic DIP
0.045 - 0.065 (1.143 - 1.651) 0.130 0.005 (3.302 0.127) 0.400 (10.160) MAX 8 7 6 5
0.250 0.010 (6.350 0.254)
1
2
3
4
N8 0392
0.018 0.003 (0.457 0.076)
TJMAX 100C
JA 130C/W
LT/GP 0592 10K REV 0
(c) LINEAR TECHNOLOGY CORPORATION 1992

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